█ Regular Sessions | █ Special Sessions | █ KeyNote & Visionary Talks |
█ Plenary Events | █ Social Events | █ Tutorials & Exhibits |
Monday, May 6th | |||
09:30 - 12:00 | TUTORIALS 1 - 2 T1. Hardware Security and Trust Verification Prabhat Mishra - University of Florida Ankur Srivastava - University of Maryland Location: International Ballroom A T2. Post-Quantum Cryptography: Implementation Attacks and Countermeasures Daniel Dinu - Intel Corporation Prasanna Ravi - Nanyang Technological University, Singapore Markku-Juhani Saarinen - Tampere University, Finland Location: Continental Ballroom | ||
12:00 - 13:00 | Break & Lunch | ||
13:00 - 14:30 | TUTORIALS 3 - 4 T3. Explainable AI for Cybersecurity Zhixin Pan - Florida State University Prabhat Mishra - University of Florida Location: International Ballroom A T4. Security of Quantum Computing Systems Jakub Szefer - Yale University Location: Continental Ballroom | ||
14:30 - 15:00 | Break | ||
15:00 - 17:30 | TUTORIALS 5 - 6 T5. Heterogeneous Integration Security Farimah Farahmandi - University of Florida Mark Tehranipoor - University of Florida Location: International Ballroom A T6. Tabletop exercise - Risks of a Trust-based Supply Chain Ahalya Sankararaman - University of Waterloo Sebastian Fischmeister - University of Waterloo Location: Continental Ballroom |
Tuesday, May 7 | |||
07:00 - 08:10 | Breakfast Location: Atrium | ||
07:30 - 17:30 | Registration | ||
08:30 - 18:00 | Exhibits Demo-Posters Location: International Ballroom B | ||
08:10 - 08:30 | Opening Remarks: HOST 2024 General and Program Chairs Location: International Ballroom A | ||
08:30 - 09:10 | Session 1: Session Chair: Mark Tehranipoor (University of Florida) Keynote Address: Greg Yeric (Director of Research, CHIPS NSTC program) Title: The CHIPS R&D Program Location: International Ballroom A | ||
09:10 - 10:10 | Session 2: Side-channel Leakage with Machine Learning
Session Chair: Fareena Saqib (UNC Charlotte)
Location: International Ballroom A
*2.1. NoiseHopper: Emission Hopping Air-Gap Covert Side Channel with Lower Probability of Detection Authors: Md Faizul Bari and Shreyas Sen *2.2. TinyPower: Side-Channel Attacks with Tiny Neural Networks Authors: Haipeng Li, Mabon Ninan, Boyang Wang and John Emmert 2.3. SNOW-SCA: ML-assisted Side-Channel Attack on SNOW-V Authors: Harshit Saurabh, Anupam Golder, Samarth Shivakumar Titti, Suparna Kundu, Chaoyun Li, Angshuman Karmakar and Debayan Das *HOST 2024 Best Paper Nominee |
||
10:10 - 10:30 | AM Break | ||
10:30 - 11:00 | Session 3: Session Chair: Kanad Basu (UT Dallas) Visionary Talk: Ophir Gaathon (Co-founder and CEO, DUST Identity) Title: Building Trust in Complex Global Supply Chains Location: International Ballroom A | ||
11:00 - 12:00 | Session 4: Pre-silicon Security Verification and Validation
Session Chair: Soheil Salehi (University of Arizona)
Location: International Ballroom A
4.1. Prioritizing Information Flow Violations: Generation of Ranked Security Assertions for Hardware Designs Authors: Avinash Ayalasomayajula, Nusrat Farzana Dipu, Debjit Pal and Farimah Farahmandi 4.2. Verifying Memory Confidentiality and Integrity of Intel TDX Trusted Execution Environments Authors: Hasini DIlanka, Debapriya Chatterjee and Prabhat Mishra 4.3. RTL-Spec: RTL Spectrum Analysis for Security Bug Localization Authors: Samit Miftah, Shamik Kundu, Mordahi Austin, Shiyi Wei and Kanad Basu |
||
12:00 - 13:00 | Lunch Break Location: Atrium | ||
13:00 - 13:40 | Session 5: Session Chair: Ankur Srivastava (University of Maryland) Keynote Address: George Orji (Deputy Director, CHIPS NAPMP) Title: CHIPS-NAPMP: Overview and Next Steps Location: International Ballroom A | ||
13:40 - 15:00 | Session 6: Hide Behind Masks
Session Chair: Naghmeh Karimi (University of Maryland, Baltimore County)
Location: International Ballroom A
6.1. Masked Memory Primitive for Key Insulated Schemes
*6.2. DOMREP II
*6.3. Security Aspects of Masking on FPGAs
6.4. Randomization approaches for Secure SAR ADC design resilient against Power Side-Channel Attacks
|
||
15:00 - 16:30 |
Session 7: PM Break + Hardware Demos + Poster Presentations
Poster Titles:
|
||
16:30 - 17:10 | Session 8: Session Chair: Ankur Srivastava (University of Maryland) Keynote Address: Dev Shenoy (OUSD R&E) Title: DoD's Microelectronics Hardware Security: Vision, Strategy, and Implementation Location: International Ballroom A | ||
17:10 - 18:00 | Exhibitors Presentations + Poster Presentations
17:15 - 17:25: JIACO
17:30 - 17:40: Riscure
|
Wednesday, May 8 | |||
07:00 - 08:10 | Breakfast Location: Atrium | ||
07:30 - 17:30 | Registration | ||
08:00 - 16:15 | Exhibits Demos Location: International Ballroom B | ||
08:30 - 11:00 | Ph.D. Dissertation challenge: Will be scheduled in parallel with the program in one of the meeting rooms Location: Atrium | ||
08:10 - 08:20 | Plenary Session Location: International Ballroom A | ||
08:20 - 09:00 | Session 9: Session Chair: Farimah Farahmandi (University of Florida) Keynote Address: Suzy Ramirez Greenberg (Vice President of Intel Product Assurance and Security and General Manager of Product Incident Response and Communications, Intel) Title: Security is a Mindset, Not Just A Feature Location: International Ballroom A | ||
09:00 - 10:00 | Session 10: Neural Network Security
Session Chair: Sazadur Rahman (University of Central Florida)
Location: International Ballroom A
10.1. QNAD: Quantum Noise Injection for Adversarial Defense in Deep Neural Networks
10.2. One Flip Away from Chaos: Unraveling Single Points of Failure in Quantized DNNs
10.3. Explainability to the Rescue: A Pattern-Based Approach for Detecting Adversarial Attacks
|
||
10:00 - 10:30 | AM Break | ||
10:30 - 11:50 | Session 11: SoCs that Don't SoC!!
Session Chair: Hadi Mardani Kamali (University of Central Florida)
Location: International Ballroom A
11.1. Empowering Hardware Security with LLM: The Development of a Vulnerable Hardware Database
11.2. LightEMU: Hardware Assisted Fuzzing of Trusted Applications
11.3. DiSPEL: A Framework for SoC Security Policy Synthesis and Distributed Enforcement
11.4. MaliGNNoma: GNN-Based Malicious Circuit Classifier for Secure Cloud FPGAs
|
||
11:50 - 13:00 | Lunch Break Location: Atrium | ||
13:00 - 14:20 | Session 12: Post-Quantum Hardware Security
Session Chair: Reza Azarderakhsh (Florida Atlantic University)
Location: International Ballroom A
12.1. A High Efficiency Hardware Design for the Post-Quantum KEM HQC
12.2. A Thorough Study of State Leakage Mitigation in Quantum Computing with One-Time Pad
12.3. A Hardware-Software Co-Design for the Discrete Gaussian Sampling of FALCON Digital Signature
12.4. Sparse Polynomial Multiplication-based High-Performance Hardware Implementation for CRYSTALS-Dilithium
|
||
14:20 - 15:50 | Session 13: Exhibits, Hardware Demo Session 2 + PM Break + Poster Presentations
Poster Titles:
|
||
15:50 - 16:30 |
Session 14:
Session Chair: Aydin Aysu (NC State University) Keynote Address: Jayson Bethurem (VP, Marketing and Business Development, Flex Logix) Title: Enable Long-Lasting SoC Security with Crypto Agility Location: International Ballroom A |
||
16:30 - 17:45 | Session 15: Panel 1
Title: Riding the Wave: The Thin Line Between Fortifying AI Hardware and Unleashing Its Potential
Moderator: Jim Plusquellic (The University of New Mexico) Panelists: Eric Breckenfeld (Nvidia) Ioannis Savidis (Drexel University) Guerney Hunt (IBM) Matt Casto (MMEC) Location: International Ballroom A | ||
17:45 - 18:30 | Break + Demos + Poster Presentations Location: International Ballroom B | ||
18:30 - 20:30 | Session 16: Banquet and Award Ceremony Location: Atrium |
Thursday, May 9 | |||
07:00 - 08:20 | Breakfast Location: Atrium | ||
07:30 - 12:30 | Registration | ||
08:20 - 08:30 | Plenary Session Location: International Ballroom A | ||
08:30 - 09:00 | Session 17:
Session Chair: Ioannis Savidis (Drexel University) Visionary Talk: Vivek Menon (Mission Assurance Director, NRO) Title: R.I.P. Logic Locking! Re-examining Threat Vectors with CHIPS Act Location: International Ballroom A |
||
09:00 - 10:20 | Session 18: System Security
Session Chair: Nektarios Tsoutsos (University of Delaware)
Location: International Ballroom A
18.1. RowHammer Cache: A Last-level Cache for Low-Overhead Row-Hammer Tracking
18.2. TrustZoneTunnel: A Cross-world Pattern History Table-based Microarchitectural Side-channel Attack
18.3. Resurrection Attack: Defeating Xilinx MPU's Memory Protection
18.4. A Security Assessment of Protected Execute-only Firmware in Microcontrollers through Selective Chemical Engraving
|
||
10:20 - 11:00 | Session 19: AM Break + Poster Presentations
|
||
11:00 - 12:00 | Session 20: Quantum and Side-Channel
Session Chair: Jiafeng "Harvest" Xie (Villanova University)
Location: International Ballroom A
20.1. Charlie, Charlie, Charlie on Industrial Control Systems: PLC Control Logic Attacks by Design, Not by Chance
20.2. Calibratable Polymorphic Temperature Sensor for Detecting Side channel and Fault Injection Attacks
20.3. Dynamic Pulse Switching for Protection of Quantum Computation on Untrusted Clouds
|
||
12:00 - 12:30 | Lunch Break Location: Atrium | ||
12:30 - 13:30 |
Session 21: Panel 2
Title: Guardians of the Chips: The Challenge in Closing the Workforce Gap Moderator: Mike Kines (OSU) Panelists: Antonio De La Serna (Siemens) Patty Schaefer (BAH) Jeyavijayan "JV" Rajendran (Texas A&M U) Adam Kimura (Battelle) Joe Sweeney (Amazon) Location: International Ballroom A |
||
13:30 - 14:50 | Session 22: Choose Your PUF Wisely!
Session Chair: Ryan Helinski (Sandia National Laboratories)
Location: International Ballroom A
22.1. SpongePUF: A Modeling Attack Resilient Strong PUF with Scalable Challenge Response Pair
22.2. PhenoAuth:A Novel PUF-Phenotype-based Authentication Protocol for IoT Devices
22.3. Machine Learning Attacks on Challenge-Response Obfuscations in Strong PUFs
22.4. Non-Invasive Attack on Ring Oscillator-based PUFs through Localized X-Ray Irradiation
|
||
14:50 - 15:00 | Concluding Remarks Program and General Chairs 2024/2025 Location: International Ballroom A |