IEEE International Symposium on Hardware Oriented Security and Trust (HOST)
May 5-8, 2025
San Jose, USA
HOST 2025 Hardware Demos
| Group Topic | Demo |
|---|---|
| Group 1: Side-Channel & Post-Quantum Cryptography | Demo 197: Side-Channel Attack on Hardware Implementation of ML-DSA in Post-Quantum Root of Trust M. Karabulut, R. Azarderakhsh |
| Demo 207: A Denoising Preprocess Method for Side-Channel Attacks Using Autoencoders M. Morita, T. Kojima, H. Ishii, H. Takase, H. Nakamura |
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| Demo 218: Bit-Level EM Side-Channel Disassembly of an 8-Bit MCU J. Park, J. Zhou, Md K. Bepary, U. Das, F. Farahmandi, M. Tehranipoor, E. Jung |
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| Demo 221: Integrating Post-Quantum Cryptography in Embedded IoT Systems B. Dong, Q. Wang |
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| Demo 229: Side-Channel Attacks in FPGA-Based Cloud Environments: Evaluating Prime+Probe Attacks V. Chadalavada, D. Aklekar, N. Lodge, F. Saqib |
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| Group 2: Hardware Trojans, IP Protection & Redaction | Demo 201: Unveiling Hardware Trojans through Side-Channel Analysis and Machine Learning A. K. John, S. T. Pitta, J. Dofe |
| Demo 208: Hidden Trigger: Interrupt-Based Hardware Trojan Exploitation A. K. John, S. T. Pitta, J. Dofe, P. Bagmare, S. G. Wooradi |
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| Demo 216: PARS: A Layered Hardware Obfuscation Platform for Resilience and Secure Collaborative Multi-Module Designs M. Hashemi, S. Mohammadi, T. E. Carlson |
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| Demo 226: Securing VLSI Subsystems using Fingerprint Biometric-Driven Logic Locking H. Aravind, M. J. E. Xavier, K. Dharsan, S. R. Mohaprasath, N. Mohankumar |
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| Demo 228: Secure Circuit Demonstration Using Logic Locking and Fault Injection on ZedBoard N. Tambe, N. Lodge, D. Aklekar, F. Saqib |
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| Demo 230: TRAP: A Transistor-Level Programmable Fabric for Cost-Effective Hardware Redaction T. Broadfoot, Y. Makris, C. Sechen |
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| Group 3: Industrial & Embedded Security | Demo 196: Firmware Attacks on Inkredible+ 3D Bioprinter M. Ahsan, J. T. Ebode, N. Lewinski, I. Ahmed |
| Demo 204: Securing PLCs with EM Side-Channels: A Non-Intrusive Approach M. S. Yaqub, R. Asmar, I. Ahmed |
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| Demo 205: EchoLogic: Audio-Based PLC Memory Monitoring for ICS Security N. Ameen, R. Vijayakanthan, A. Ayub, A. Ali-Gombe, I. Ahmed |
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| Demo 232: Power Distribution Network-Based Runtime Anomaly Detection for Embedded System Security K. Chen, X. Guo, X. Feng |
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| Group 4: PUFs, TRNGs & Hardware Authentication | Demo 219: ResCav System: Non-Destructive Microwave Resonant Cavity Technique for Integrated Circuit Authentication A. Nechiyil, R. Lee, G. Chapman |
| Demo 223: S3: Securing Supposed-to-be Secure Hardware Primitives H. I. Reefat, H. Pourmehrani, M. Ebrahimabadi, J. Bahrami, Md T. H. Anik, S. Guilley, J-.L Danger, N. Karimi |
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| Demo 224: A TRNG Implemented using a Soft-Data Based Sponge Function within a Unified Strong PUF Architecture R. Cazzola, J. Plusquellic, C. Minwalla, C. Chan |
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| Demo 225: Sourcing Trust From Peers with Physical Unclonable Functions Md S. Siraj, A. B. Rahman, E. E. Tsiropoulou, C. Minwalla, J. Plusquellic |
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| Group 5: AI and Learning-based Security | Demo 217: ArduiGlitch - A learning tool to introduce power-glitch-induced instruction skips into microcontrollers H. Perrin, J.-M. Dutertre, J-. B. Rigaud |
| Demo 220: Standardizing Security Assurance for IPs using SA-EDI and CWE A. Uddin, Md A. Hasan, N. Alam, S. K. Saha, F. Farahmandi, M. Tehranipoor |
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| Demo 222: SV-LLM: An Agentic LLM Framework for Hardware Security Verification D. Saha, H. Al Shaikh, S. Tarek, P. S. Nalluri, K. T. Hasan, R. Guo, Md A. Hasan, S. K. Saha, J. Zhou, M. Tehranipoor, F. Farahmandi |
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| Demo 227: Byzantine Data Poisoning: Hardware Implementation Weakening Federated Learning Security N. Lodge, V. Chadalavada, N. Tambe, F. Saqib |
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| Demo 231: LLM assisted Information Flow Tracking for the RISC-V architectures D. Aklekar, V. Chadalavada, N. Tambe, F. Saqib |
