Presenter Information

Mark M. Tehranipoor is currently the Intel Charles E. Young Preeminence Endowed Chair Professor and the Chair of the Department of Electrical and Computer Engineering (ECE) at the University of Florida. His current research projects include: hardware security and trust, supply chain security, IoT security, VLSI design, test and reliability. He is a recipient of a dozen best paper awards and nominations, as well as the 2008 IEEE Computer Society (CS) Meritorious Service Award, the 2012 IEEE CS Outstanding Contribution, the 2009 NSF CAREER Award, and the 2014 AFOSR MURI award. He received the 2020 University of Florida Innovation of the year as well as teacher/scholar of the year awards. He co-founded the IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE). He serves on the program committee of more than a dozen leading conferences and workshops. He has also served as Program and General Chair of a number of IEEE and ACM sponsored conferences and workshops (HOST, ITC, DFT, D3T, DBT, NATW, and more). He is currently serving as a founding EIC for Journal on Hardware and Systems Security (HaSS) and served as Associate Editor for TC, JETTA, JOLPE, TODAES, IEEE D&T, TVLSI. He is currently serving as a founding director for Florida Institute for Cybersecurity Research (FICS) and a number of other centers with focus on microelectronics security. Dr. Tehranipoor is a Fellow of the IEEE, a Fellow of the ACM, a Fellow of the National Academy of Inventors (NAI), a Golden Core Member of IEEE CS, and Member of ACM SIGDA.

Farimah Farahmandi is the Wally Rhines Endowed Professor in the Department of Electrical and Computer Engineering (ECE) and the associate director of Edaptive Computing Inc., Transition Center (ECI-TC), and Florida Institute for Cybersecurity (FICS) at the University of Florida. She received her Ph.D. from the Department of Computer and Information Science and Engineering (CISE) at the University of Florida, 2018. Her research interests include hardware security verification, formal methods, fault-injection attack analysis, side-channel leakage assessment, information leakage, secure physical design, secure supply chain of microelectronics, and post-silicon validation and debug. Her research has resulted in five books, nine book chapters, and several publications in premier ACM/IEEE journals and conferences. She is the recipient of the 2022 Semiconductor Research Corporation Young Faculty Award and 2022 ECE Research Excellence Award at UF. She is also the recipient of four best paper nominations from IEEE/ACM ASPDAC and IEEE/ACM DATE. She currently serves as an Associate Editor of IET Computers & Digital Techniques. She is the program chair of IEEE HOST 2023. Her research has been sponsored by SRC, DARPA, AFRL, DoD, Synopsys, Analog Devices, ANSYS, and Cisco.

Overview

Modern System-on-Chip (SoC) designs now power an ever-expanding range of devices—from smartphones and IoT gadgets to autonomous vehicles and cloud servers—bringing unprecedented levels of functionality and integration. However, as these systems incorporate numerous third-party IPs and increasingly complex interactions, ensuring their security becomes a formidable challenge. Traditional verification methods, which are often manual, narrowly focused, or labor-intensive, struggle to keep pace with the growing sophistication and dynamic threat landscape of modern SoCs.

At the same time, large language models (LLMs) have rapidly evolved, demonstrating exceptional capabilities in natural language understanding, code generation, and complex reasoning. These models have already transformed fields such as text generation, summarization, and even specialized domain applications like healthcare and legal analysis. Their ability to learn from limited examples and adapt to new information positions them as promising tools for automating and enhancing security verification processes in hardware design.

In this tutorial, we present how LLMs can be harnessed to automate and improve various phases of SoC security verification. We will explore use cases ranging from identifying security assets and automating test plan generation to detecting vulnerabilities and generating secure designs, while also discussing an “agentic” approach in which multiple LLM-based agents will work together to automate complex security verification tasks. A demonstration of SV Chat will showcase these concepts in practice. Ultimately, our goal is to provide a comprehensive overview of the evolving SoC security landscape, dive deep into LLM-assisted security verification tasks, and outline a roadmap for integrating LLMs into robust, scalable verification workflows.

Prerequisites and Required Materials

• Basic knowledge of SoC design flow
• Basic hardware security knowledge