Congratulations 2017 Accepted Papers!


Regular Papers

Paper ID TITLE
4 Secure Heterogeneous Multicore Architecture Design
5 Characterising a CPU Fault Attack Model via Run-Time Data Analysis
7 Automatic Generation of High-Performance Modular Multipliers for Arbitrary Mersenne Primes on FPGAs
9 Exploring Timing Side-channel Attacks on Path-ORAMs
19 Creating Security Primitive by Nanoscale Manipulation
40 A New Maskless Debiasing Method for Lightweight Physical Unclonable Functions
42 Using Computational Game Theory To Guide Verification and Security in Hardware Designs
56 When Good Protections Go Bad: Exploiting Anti-DoS Measures to Accelerate Rowhammer Attacks
57 Stateless Leakage Resiliency from NLFSRs
61 Take a Moment and have some t: Hypothesis Testing on Raw PUF Data
64 Intrinsic Rowhammer PUFs: Leveraging the Rowhammer Effect for Improved Security
69 Physical Unclonable Functions and Dynamic Partial Reconfiguration for Security in Resource-Constrained Embedded Systems
70 Efficient Configurations for Block Ciphers with Unified ENC/DEC Paths
72 High Efficiency Power Side-Channel Attack Immunity using Noise Injection in Attenuated Signature Domain
91 AppSAT: Approximately Deobfuscating Integrated Circuits
111 New Clone-Detection Approach for RFID-Based Supply Chains
128 Reviving Instruction Set Randomization
130 A Stochastic All-Digital Weak Physically Unclonable Function for Analog/MixedSignal Applications

Short Papers

Paper ID TITLE
23 Breaking Hardware-Assisted Flow Integrity Extension
24 Memory-Constrained Implementation of Lattice-based Encryption Scheme on Standard Java Card
31 A Novel Physiological Features-Assisted Architecture for Rapidly Distinguishing Health Problems from Hardware Trojan Attacks and Errors in Medical Devices
43 Towards a Memristive Hardware Secure Hash Function (MemHash)
58 INFECT: INcospicious FEC-based Trojan: a Hardware Attack on an 802.11a/g Wireless Network
98 Challenging On-Chip SRAM Security with Boot-State Statistics
104 Improving Reliability of Weak PUFs via Circuit Techniques to Enhance Mismatch
115 Photonic Side Channel Attacks Against RSA

Poster Presentations

Paper ID TITLE
3 Ag Conductive Bridge RAMs for Physical Unclonable Functions
8 Fabrication Security and Trust of Domain-Specific ASIC Processors
21 Øzone: Efficient Execution with Zero Timing Leakage for Modern Microarchitectures
25 LWE-Based Lossless Computational Fuzzy Extractor for the IoT
28 Cache Timing Attacks on Recent Microarchitectures
35 Analyzing Security Vulnerabilities of Three-Dimensional Integrated Circuits
37 A Novel Offset Method for Improving Bitstring Quality of a Hardware-Embedded Delay PUF
45 Malicious CAN-message Attack against Advanced Driving Assistant System
50 Efficient FPGA Implementation of the SHA-3 Hash Function
54 On Secure Implementations of Quantum-Resistant Supersingular Isogeny Diffie-Hellman
60 Protecting Analog Circuits with Parameter Biasing Obfuscation
63 Circuit Recognition with Deep Learning
78 Detection of Counterfeit ICs using Public Identification Sequences
90 Threshold Voltage Defined Multi-Input Camouflaged Gate
95 Platform Agnostic, Scalable, and Unobtrusive FPGA Gateway Implementation of Moving Target Defense over IPv6 (MT6D)
100 TTLock: Tenacious and Traceless Logic Locking
101 Exploiting Safe Error Based Leakage of RFID Authentication Protocol using Hardware Trojan Horse
112 Characterizing EEPROM for usage as a ubiquitous PUF source
113 On Designing Optimal Camouflaged Layouts
121 Connecting the Dots: Privacy Leakage via Write-Access Patterns to the Main Memory
124 Correlation Power Analysis Attack against STT-MRAM Based Cyptosystems
126 Synthesis of Hardware Sandboxes for Trojan Mitigation in Systems on Chip