Congratulations 2018 Accepted Papers!


Regular Papers

Paper ID TITLE
3 Syndrome: Spectral Analysis for Anomaly Detection on Medical IoT and Embedded Devices
4 B-TREPID: Batteryless Tamper-Resistant Envelope with a PUF and Integrity Detection
17 TZSlicer: Security-Aware Dynamic Program Slicing for Hardware Isolation
36 Secure Chip Odometers Using Intentional Controlled Aging
39 Independent Detection of Recycled Flash Memory: Challenges and Solutions
40 A Compact Energy-Efficient Pseudo-Static Camouflaged Logic Family
42 Zero-Permission Acoustic Cross-Device Tracking
56 Horizontal Side-Channel Vulnerabilities of Post-Quantum Key Exchange Protocols
57 CTCG: Charge-Trap Based Camouflaged Gates for Reverse Engineering Prevention
60 Remote Attestation of IoT Devices via SMARM: Shuffled Measurements Against Roving Malware
62 Fault-Assisted Side-Channel Analysis of Masked Implementations
78 Fresh Re-Keying with Strong PUFs: A New Approach to Side-Channel Security
84 An Efficient SAT-Based Algorithm for Finding Short Cycles in Cryptographic Algorithms
90 The CAESAR-API in the Real World - Towards a Fair Evaluation of Hardware CAESAR Candidates
93 Dividing the Threshold: Multi-Probe Localized EM Analysis on Threshold Implementations
96 Large Scale RO PUF Analysis over Slice Type, Evaluation Time and Temperature on 28nm Xilinx FPGAs
107 Direct Read of Idle Block RAM from FPGAs Utilizing Photon Emission Microscopy

Poster/Short Papers

Paper ID TITLE
7 Value Prediction for Security (VPsec): Countering Fault Attacks in Modern Microprocessors
13 Securing Interconnected PUF Network with Reconfigurability
16 Robust, Low-Cost, and Accurate Detection of Recycled ICs using Digital Signatures
23 Abnormal Vehicle Behavior Induced Using Only Fabricated Informative CAN Messages
25 R2D2: Runtime Reassurance and Detection of A2 Trojan
27 A Flexible Leakage Trace Collection Setup for Arbitrary Cryptographic IP Cores
28 Lowering the Barrier to Online Malware Detection Through Low Frequency Sampling of HPCs
34 SIN2: Stealth Infection on Neural Network – A Low-cost Agile Neural Trojan Attack Methodology
48 Repurposing SoC Analog Circuitry For Additional COTS Hardware Security
49 Comparison of Cost of Protection Against Differential Power Analysis of Selected Authenticated Ciphers
54 On State Encoding Against Power Analysis Attacks for Finite State Controllers
55 Delay Model and Machine Learning Exploration of a Hardware-Embedded Delay PUF
65 FPGA-Oriented Moving Target Defense against Security Threats from Malicious FPGA Tools
71 RF-PUF: IoT Security Enhancement through Authentication of Wireless Nodes using In-situ Machine Learning
72 Energy Efficient and Side-Channel Secure Hardware Architecture for Lightweight Cipher SIMON
73 Chaos Computing for Mitigating Side Channel Attack
75 SAT-based Reverse Engineering of Gate-Level Schematics using Fault Injection and Probing
79 Self-Authenticating Secure Boot for FPGAs
91 Protecting Block Ciphers against Differential Fault Attacks without Re-keying
111 Inverse Gating for Low Energy Encryption