IEEE International Symposium on Hardware Oriented Security and Trust (HOST)
In Person HOST Symposium
June 27 - 30, 2022
Washington DC, USA
HOST 2022 Tutorial Program, June 27, 2022
| 12:30 - 13:00 | Registration |
| 13:00 - 15:30 | TUTORIALs 1 ~ 3 T1. CAD for SoC Security Verification Mark Tehranipoor (bio) - University of Florida Farimah Farahmandi (bio) - University of Florida Location: Continental ABC Abstract: The growing complexity of system-on-chips (SoCs) and the ever-increasing cost of IC fabrication have forced the semiconductor industry to shift from a vertical business model to a horizontal model. In this model, time-to-market and manufacturing costs are lowered through outsourcing and design reuse. To be more specific, SoC designers obtain licenses for third party intellectual property (3PIPs) and integrate them with their in-house IPs to design a specific SoC. To further reduce the cost, they may also outsource the SoC design to contract design houses, foundries, and assemblies for synthesis, DFT insertion, GDSII development, fabrication, test, and packaging. With most of these entities involved in design, manufacturing, integration, and distribution located across the globe, SOC design houses no longer have the ability to monitor the entire process and ensure security and trust. Moreover, designers are not knowledgeable about all vulnerabilities in the design, and the countermeasures to address them. Unfortunately, existing tools do not help with the alleviating the magnitude of the problem. The tools are developed to optimize designs against power, performance, and area, while security is completely ignored. In fact, in some cases, tools and designers unintentionally create vulnerability in a circuit through security-unaware design processes/practices. These issues and the lack of trust and control have led to a large number of vulnerabilities. Hence, it is imperative to develop computer-aided design (CAD) tools with security in mind to identify and address vulnerabilities through design life-cycle. To protect the SoC from such vulnerabilities, academic and industry researchers have proposed many design-for-security and security assessment/validation techniques, e.g., information flow tracking, side-channel leakage analysis, IP encryption, logic obfuscation, design-for-anticounterfeit, etc. These techniques can be applied to detect vulnerabilities in ASIC and FPGA design flows. Some of these techniques are currently being evaluated by industry and are expected to be adopted in the near future. However, recent literature has pointed out to some of the limitations of these approaches. Therefore, it is crucial to have an in-depth understanding of the security provided by different techniques and understand their limitations. The goal of this tutorial is to present (i) the threat posed by each entity in the SoC supply chain, (ii) vulnerabilities introduced during various stages of design life-cycle, (iii) CAD tools and methodologies for security assessment, (iv) Countermeasure tools and methodologies for addressing each vulnerability, and (vi) challenges and research roadmap ahead. T2. Side Channel Analysis: from Concepts to Simulation and Silicon Validation Gang Qu (bio) - University of Maryland, College Park Norman Chang (bio) - ANSYS Lang Lin (bio) - ANSYS Location: Beverly Abstract: Since the report of simple and differential power analysis in the late 1990’s, side channel analysis (SCA) has been one of the most important and well-studied topics in hardware security. In this tutorial, we will share our insights and experience on SCA by a combination of presentations, embedded demos, and an interactive panel discussion. The three speakers are from academia and industry with rich experience and solid tracking record on hardware security research and practice. We will start the tutorial with a comprehensive introduction of SCA, including the popular side channels that have been exploited by attackers, common countermeasures, and the simulation based SCA with commercial EDA tools. Then we will present industry proven flows for fast and effective pre-silicon side channel leakage analysis (SCLA) with focus on physical level power and electromagnetic (EM) side channels. Next, we elaborate how to perform on-chip and in-system side-channel leakage measurements and assessments with system-level assembly options on crypto silicon chips with the help of embedded on-chip noise monitor circuits. We will conclude the presentations with some forward-looking discussion on emerging topics such as SCA for security, SCA in AI and machine learning (ML), and pre-silicon SCLA assisted by AI/ML. Short video clips will be embedded to showcase SCA by simulation and silicon measurement. No prior knowledge is required to attend this tutorial. The audience is expected to learn the foundations and state-of-the-arts in SCA with some hands-on skills. T3. Hardware Trust Validation Using Machine Learning and Formal Methods Shobha Vasudevan (bio) - UIUC & Google Brain Prabhat Mishra (bio) - University of Florida Location: Dallas Abstract: This tutorial provides an overview of recent advances in hardware security and trust validation using simulation-based approaches, formal methods, and machine learning. Specifically, the tutorial consists of three parts. The first part introduces security vulnerabilities and trust validation challenges. It also highlights the recent advances in developing trust metrics and benchmarks. The second part covers ML-based approaches for assertion generation, coverage analysis, and mitigation of hardware security vulnerabilities. The third part describes hardware vulnerability analysis using formal verification. It concludes with a discussion on how to integrate security verification into the existing functional validation methodology. |
| 15:30 - 16:00 | Coffee Break Location: Atrium |
| 16:00 - 17:30 | TUTORIALs 4 and 5 T4. Designing and Building More Secure Hardware with CWE Jason Oberg (bio) - Cycuity Alec Summers (bio) - MITRE Jason Fung (bio) - Intel Location: Continental ABC Abstract: Common Weakness Enumeration (CWE™) was first introduced in 2006 as a community-developed method for cataloging security weaknesses in software to provide a consistent language for the industry to talk about the root-cause mistakes that lead to vulnerabilities. By providing a public list of common software weaknesses, the software industry widely adopted CWE to prioritize the weaknesses that were most relevant for their products, effectively ranking the highest impact weaknesses, and ultimately providing the basis of building a security development lifecycle for software. The use of CWE continues to become more pervasive in the software security community. In February 2020, CWE expanded its scope into hardware weaknesses for the first time. It currently enumerates close to 100 hardware weaknesses across 12 different categories and is a promising start to provide an industry-aligned initiative to build more secure hardware. However, there is much for the industry to learn to use CWE effectively. This tutorial’s goal is to provide guidance on how to effectively use CWE to build more secure hardware and to foster more collaboration and participation in the initiative. T5. Physical Inspection for Hardware Assurance Navid Asadizanjani (bio) - University of Florida Location: Beverly Abstract: In this tutorial we will focus on the physical inspections, physical attacks, reverse engineering, counterfeit detection, advanced and heterogenous package security, etc. of electronics from the device to system level using advanced microscopy, failure analysis (FA) techniques combined with image analysis and machine learning. We first introduce the advanced techniques for physical inspection and failure analysis on electronic systems and components. More than five different modules will be discussed here to cover different aspects of the topic. The most recent techniques for physical inspection and attacks are based on the tools and methodologies developed for FA in electronics. FA tools are primarily developed to detect a defect during or after fabrication process, but they have good enough resolution to detect Trojans, extract secret keys, or reverse engineer IC if used maliciously. Such tools include different imaging modalities such as optical microscope, scanning electron microscope (SEM), focused ion beam (FIB), photon emission microscope (PEM), X-ray microscopy (XRM), etc. and probe stations. It is worth mentioning that these attacks require a very sophisticated sample preparation process to expose a targeted area for reverse engineering or other measurements. The attendees will learn the basics of how such advanced microscopes are working and how they are used for physical inspection approaches including: reverse engineering, counterfeit detection, invasive and semi-invasive attacks, on electronics from device to system level. |
