Rapid proliferation of computing and communication systems with increasing computational power and connectivity into every sphere of modern life has brought security to the forefront of system design, test, and validation processes. The emergence of new application spaces for these systems in the internet-of-things (IoT) regime is creating new attack surfaces as well as new requirements for secure and trusted system operation. Additionally, the design, manufacturing and the distribution of microchip, PCB, as well as other electronic components are becoming more sophisticated and globally distributed with a number of potential security vulnerabilities. Therefore, hardware plays an increasingly important and integral role in system security with many emerging system and application vulnerabilities and defense mechanisms relating to hardware. IEEE International Symposium on Hardware Oriented Security and Trust (HOST) aims to facilitate the rapid growth of hardware-based security research and development. HOST highlights new results in the area of hardware and system security. Relevant research topics include techniques, tools, design/test methods, architectures, circuits, and applications of secure hardware.

Call for Paper

• Hardware security primitives (Crypto, PUFs, RNGs)
• Hardware design techniques to facilitate software and/or system security
• Architecture support for security
• Side-channel analysis, attacks, and protection
• Hardware Trojan attacks, detection, and countermeasures
• Hardware security test and verification
• IoT, automotive, and cyber-physical system security
• FPGA and system-on-chip (SoC) security
• Supply chain risk mitigation (e.g., counterfeit detection & avoidance)
• Reverse engineering and hardware obfuscation
• Fault injection and mitigation
• Metrics, policies, assessment, and standards related to hardware security
• Hardware IP trust (watermarking, metering, trust verification)
• Trusted manufacturing including split manufacturing and 2.5/3D integration
• Hardware tampering attacks and protection
• Design and applications of emerging and nanoscale devices for security
• Sensor-enabled hardware security
• Machine learning for hardware security
• Hardware acceleration for security applications
• Applications of cyber deception in hardware security
• Privacy-preserving computing, secure function evaluation
• Architecture and hardware-enabled SoC, cyber, data center, etc. security

You can register (by October 9, 2017, 11:59 p.m. (PST)) and submit (by October 23, 2017, 11:59 p.m. (PST)) your paper at https://easychair.org/conferences/?conf=host2018. The page limit is 8 pages, double column, IEEE format, with a minimum font size of 10 pt. Authors will be asked if they want their paper to be considered for a 4-page poster paper (if it is not accepted as a full paper). Note that poster papers will be considered as publications. The paper selection will involve a double blind review process. Therefore, the identity of authors must not be revealed, directly or indirectly, anywhere in the manuscript. Only work that has not been previously published at the time of the conference will be considered. Duplicate submissions to concurrent conferences are not permissible, and if encountered will be rejected and reported to IEEE.

Awards and Travel Grants

Top papers will be considered for best paper awards. For the best student paper award, the paper’s first author and presenter must be a full-time student. Travel grants are available for graduate and undergraduate students.

Click here for a list of important dates