Paper ID | TITLE |
8 | Improving on State Register Identification in Sequential Hardware Reverse Engineering |
12 | Laser-induced Single-bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller |
13 | In-depth Analysis and Enhancements of RO-PUFs with a Partial Reconfiguration Framework on Xilinx Zynq-7000 SoC FPGAs |
15 | A Fetching Tale: Covert Communication With The Hardware Prefetcher |
18 | MPCircuits: Optimized Circuit Generation for Secure Multi-Party Computation |
25 | RATAFIA: Ransomware Analysis using Time And Frequency Informed Autoencoders |
27 | CoPHEE: Co-processor for Partially Homomorphic Encrypted Execution |
34 | Detecting Recycled SoCs by Exploiting Aging Induced Biases in SRAM Cells |
36 | Using Hardware Software Codesign for Optimised Implementations of High-Speed and Defence in Depth CEASAR Finalists |
40 | STELLAR: A Generic EM Side-Channel Attack Protection through Ground-Up Root-cause Analysis** |
52 | Securing AES against Localized EM Attacks through Spatial Randomization of Dataflow |
58 | A Statistical Fault Analysis Methodology for the Ascon Authenticated Cipher |
63 | SURF: Joint Structural Functional Attack on Logic Locking |
67 | SIA: Secure Intermittent Architecture for Off-the-Shelf Resource-Constrained Microcontrollers |
73 | ENTT: A Family of Emerging NVM-based Trojan Triggers |
75 | Extracting side-channel leakage from round unrolled implementations of lightweight ciphers |
81 | FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection |
82 | QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment |
83 | Golden Gates: A New hybrid Approach for Rapid Hardware Trojan Detection using Testing and Imaging## |
88 | Exploiting Proximity Information in a Satisfiability Based Attack Against Split Manufactured Circuits |
91 | High Capability and Low-Complexity: Novel Fault Detection Scheme for Finite Field Multipliers over $GF(2^m)$ based on MSPB## |
98 | COTSknight: Practical Defense against Cache Timing Channel Attacks using COTS Hardware |
102 | Efficient and Flexible Low-Power NTT for Lattice-Based Cryptography |
108 | Using Power-Anomalies to Counter Evasive Micro-architectural Attacks in Embedded Systems** |
110 | On the Impossibility of Approximation-Resilient Circuit Locking |
** HOST 2019 Best Paper and Best Student paper Nominee
## HOST 2019 Best Paper Nominee