| ID |
TITLE |
| 72 |
Large Laser Spots and Fault Sensitivity Analysis |
| 110 |
UCR: Unclonable Chipless RFID Tag |
| 27 |
A Key-centric Processor Architecture for Secure Computing |
| 111 |
Robust Privacy-preserving Fingerprint Authentication |
| 116 |
A Layout-driven Framework to Assess Vulnerability of ICs to Microprobing Attacks |
| 43 |
A New Approach for Rowhammer Attacks |
| 49 |
An Area Optimized Serial Implementation of ICEPOLE Authenticated Encryption Scheme |
| 60 |
A Highly Reliable and Tamper-Resistant RRAM PUF: Design and Experimental Validation |
| 96 |
Machine Learning Resistant Strong PUF: Possible or a Pipe Dream? |
| 121 |
Parsimonious Design Strategy for Linear Layers with High Diffusion in Block Ciphers |
| 35 |
LEDPUF: Stability-Guaranteed Physical Unclonable Functions through Locally Enhanced Defectivity |
| 74 |
GenMatch: Secure DNA Compatibility Testing |
| 130 |
A Zero-cost Approach to Detect Recycled SoCs Using Embedded SRAM |
| 59 |
IP Core Protection using Voltage-Controlled Side-Channel Receivers |
| 5 |
Hardware Security Risk Assessment: A Case Study |
| 14 |
Redirecting DRAM Memory Pages: Examining the Threat of System Memory Hardware Trojans |
| 21 |
Iterating Von Neumann's Post-Processing under Hardware Constraints |
| 85 |
A Separation and Protection Scheme for On-chip Memory Blocks in FPGAs |
| 44 |
Hardware-based Workload Forensics: Process Reconstruction via TLB Monitoring |
| 107 |
Controlling your Control Flow Graph |
| 113 |
Round Gating for Low Energy Block Ciphers |
| 13 |
A Secure Camouflaged Threshold Voltage Defined Logic Family |
| 58 |
Classification Algorithms for Template Matching |
| 65 |
SARLock: SAT Attack Resistant Logic Locking |
| 66 |
The Other Side of The Coin: Analyzing Software Encoding Schemes Against Fault Injection Attacks |
| 98 |
A Novel Security Technique for Generating Truly Random and Reliable Reconfigurable ROPUF-Based Cryptographic Keys |
