The Trusted and Assured MicroElectronics Forum

The Trusted and Assured MicroElectronics Forum (TAME) brings together experts to discuss (i) various challenges in protecting electronics supply chain in design stage and throughout lifecycle for SoCs, microprocessors, microcontroller, FPGAs, and analog and mixed-signal components, (ii) develop tools, technologies and practices to design of vulnerability-free microelectronics, (iii) develop technologies and architectures for security hardening and resilience, and (iv) establishing secure design environments in today’s globalized and complex design processes and supply chain. Finally, TAME aims to tackle security and assurance issues for legacy parts, active parts, and new parts by including innovative design for security concepts.

Topics to be covered by TAME includes but no limited to:

  • Supply chain vulnerability analysis and risk mitigation
  • Counterfeit detection and avoidance
  • Hardware security primitives (Crypto, PUFs, RNGs)
  • Architecture support for security
  • Side-channel analysis, attacks, and protection
  • Hardware tampering attacks, detection, and countermeasures
  • Hardware security test and verification
  • FPGA and system-on-chip (SoC) security
  • Reverse engineering and hardware obfuscation
  • Metrics, policies, assessment, and standards related to hardware security
  • Hardware IP trust (watermarking, metering, trust verification)
  • Trusted manufacturing including split manufacturing and 2.5/3D integration

The forum is open to public, and will feature experts from industry, academia, and government.


Time: May 3 & 4, 2018

Location: The Ritz-Carlton, McLean, VA, USA [Co-located with HOST 2018]


>> Click here to visit the TAME Forum website <<


Workshop Program:

Thursday, May 3
11:00 – 12:00 TAME registration for HOST attendees
12:00 – 13:15 Registration for TAME-only attendees
SESSION I
Session Chair: Brian Dupaix, Air Force Resarch Laboratory (AFRL)
13:15 – 13:30 Introductory and Welcome Remarks
13:30 – 14:15 KEYNOTE
Speaker: Kristen J. Baldwin, Acting Deputy Assistant Secretary, Defense Systems Engineering
14:15 – 15:00 VISIONARY TALK
Speaker: Sanidp Kundu, Program Manager, NSF; Professor of Electrical & Computer Engineering, University of Massachusetts, Amherst
15:00 – 15:30 BREAK
SESSION II - Panel Discussion
Session Chair: Brian Cohen, Institute of Defense Analysis (IDA)
15:30 – 16:30 Panel on TAME Mission and Roadmap
Panel Moderator: Brian Cohen, Institute of Defense Analysis (IDA)
16:30 – 18:00 Breakout Session Reporting
Panel Moderator: Brian Cohen, Institute of Defense Analysis (IDA)
SESSION III - Social Event
18:00 Reception
Friday, May 4
7:00 – 8:00 Continental Breakfast
SESSION I - Panel Discussion
Session Chair: Waleed Khalil, Ohio State University
8:00 – 9:15 Topic: 10 Years of Hardware Security Research: Is It All Hype or Steady Progress?
Panel Moderator: Waleed Khalil, Ohio State University
9:15 – 9:45 BREAK
9:45 – 12:00 Breakout Sessions
Session 1 Designed-in Security and Trust
Lead: Matt Casto (AFRL)
Scribe: John Hallman (MacB)
This group will discuss the grand challenges related to security and trust in the design phase with particular attention to how you can secure design processes against malicious action and what new design capabilities and architectures might be needed to support future secure systems and missions.
Session 2 National Hardware Vulnerability Database
Lead: Robert Martin (MITRE)
Scribe: Ken Heffner (Honeywell)
This group will discuss the motivation and benefit of having a national vulnerabilities database as well the challenges in creating such a database and what kind of plan of action might be needed to make it happen.
Session 3 National Technology Roadmap for Trusted and Assured Microelectronics
Lead: Ezra Hall (GlobalFoundries)
Scribe: Anita Balachandra (Techvision21)
This group will discuss the potential for creating a roadmap, leveraging the discussion in the previous panel. The discussion should consider the purpose for the roadmap, who would be the audience and develop recommendations on a plan of action for creating such a roadmap.

Contact Information

Yousef Iskander, Cisco

E-mail: yiskande at cisco.com