Mr Serge Leef

Serge Leef Bio: Mr. Serge Leef joined DARPA in August 2018 as a program manager in the Microsystems Technology Office (MTO). His research interests include computer architecture, simulation, synthesis, semiconductor intellectual property (IP), cyber-physical modeling, distributed systems, secure design flows, and supply chain management. He is also interested in the facilitation of startup ecosystems and business aspects of technology. Leef came to DARPA from Mentor, a Siemens Business where from 2010 until 2018 he was a Vice President of New Ventures, responsible for identifying and developing technology and business opportunities in systems-oriented markets. Additionally, from 1999 to 2018, he served as a division General Manager, responsible for defining strategies and building successful businesses around design automation products in the areas of hardware/software co-design, multi-physics simulation, IP integration, SoC optimization, design data management, automotive/aerospace networking, cloud-based electronic design, Internet of Things (IoT) infrastructure, and hardware cybersecurity. Prior to joining Mentor, he was responsible for design automation at Silicon Graphics, where he and his team created revolutionary, high-speed simulation tools to enable the design of high-speed 3D graphics chips, which defined the state-of-the-art in visualization, imaging, gaming, and special effects for a decade. Prior to that, he managed a CAE/CAD organization at Microchip and developed functional and physical design and verification tools for major 8- and 16-bit microcontroller and microprocessor programs at Intel. Leef received his Bachelor of Science degree in electrical engineering and Master of Science degree in computer science from Arizona State University. He has served on corporate, state, and academic advisory boards, delivered numerous public speeches, and holds two patents.

Title: Automatic Implementation of Secure Silicon

Abstract: Throughout the past decade, cybersecurity threats have evolved from attacks focused high in the software stack to progressively lower levels of computational hierarchy. With the explosion of popularity and growing deployment of internet connected devices, economic attackers and nation-states alike are shifting their attention to Application Specific Integrated Circuits (ASICs) that enable complex capabilities across commercial and military application domains. Despite growing recognition of the problem and a substantial body of research across multiple chip security areas, no common tools, methods or solutions are in wide use today. Modern synchronous digital ASICs are already very complex and expensive to design and incorporation of security is viewed as a burden with unclear economic benefits. The result is that the majority of today’s ASICs are largely unprotected. Absence of automation makes incorporation of security a laborious, manual task that generally requires very specific design expertise not generally possessed by semiconductor companies. These dynamics can be altered with a novel chip design flow that aims to protect advanced ASICs from known attack strategies by streamlining inclusion of scalable defense mechanisms into an automated process that maximizes architectural exploration of security vs. economics trade-offs while improving design productivity. The effort and cost to incorporate a level of hardware security aligned with application requirements and economics will be significantly reduced so that incorporation of security at all levels of hardware design is feasible and affordable.